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Describe common RTL lint warnings and errors

AppleSoftware Engineer · Technical Screen
MediumSoftware EngineerTechnical ScreenSoftware Engineering Fundamentals

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This question evaluates understanding of RTL static analysis and common lint warnings/errors in Verilog/SystemVerilog, testing competence in diagnosing issues such as modules treated as black boxes, combinational loops, and width mismatches.

You are writing RTL (e.g., Verilog/SystemVerilog) and run a lint tool on your code.

The tool reports items such as:

  • "Treat as black box"
  • Combinational loop
  • Left-hand side (LHS) / right-hand side (RHS) not equal length (width mismatch)

Explain for each of these:

  1. What situation usually causes the warning or error.
  2. Why it can be dangerous if left unfixed.
  3. Typical ways you would investigate and fix the issue in your RTL.

Also briefly describe why running lint is important in a digital design flow.