Schedule instructions on a VLIW pipeline

On a 4-issue VLIW machine with two ALUs, one load/store unit, and one special-function unit, and with latencies ALU=1 cycle, load=3 cycles, special=2 cycles, schedule a given basic block represented as a dependency DAG to maximize parallel issue and minimize stalls. Produce a legal instruction schedule, explain your handling of hazards and register pressure, discuss software pipelining for a looped version, and describe how your schedule changes if average memory latency increases by one cycle.