Optimize CUDA GEMM with tiling and coalescing
NVIDIAData Scientist · HR Screen
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This question evaluates proficiency in GPU programming and performance optimization, assessing understanding of the CUDA execution model, memory hierarchy and bank conflicts, occupancy limits, and practical kernel design concerns for single-precision GEMM including tiling, coalescing, vectorized memory accesses and benchmarking.
Explain CUDA’s execution model (grid, blocks, warps, threads), memory hierarchy (global, shared, registers, constant/texture), and occupancy. Then design an efficient single‑precision GEMM kernel C=A×B: start with a naive kernel; optimize with tiling and shared memory, coalesced loads/stores, avoiding bank conflicts, loop unrolling, and vectorized accesses. Choose grid/block sizes, handle non‑multiple tile edges, and compare throughput to a cuBLAS baseline. How would you overlap host‑device transfers with compute (streams, pinned memory) and measure achieved occupancy, arithmetic intensity, and memory bandwidth?
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