Explain Virtual Memory, MMUs, and TLBs
Hudson River TradingSoftware Engineer · Onsite
Last updated
Trace a virtual-memory load through TLB lookup, page-table walking, MMU permission checks, cache and physical access, page-fault handling, context switches, huge pages, and cross-core shootdowns.
Walk through what happens when a process loads from a virtual address. Explain the roles of page tables, the memory-management unit, the translation lookaside buffer, page faults, protection bits, and context switches.
Constraints & Assumptions
- Separate address translation from cache lookup and physical memory access.
- Distinguish a TLB miss from a page fault.
- Acknowledge that exact page-table formats and cache ordering vary by architecture.
Clarifying Questions to Ask
- Which architecture and page size should be assumed?
- Is the page resident, swapped out, or unmapped in the scenario?
- Does the question include multi-core TLB shootdowns?
Follow-up questions
- Why can a program have many TLB misses without any page faults?
- How do huge pages change TLB reach and fragmentation?
- What must happen when one core changes a page-table entry used by other cores?
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