Explain Cache Conflicts and Related Memory-Access Problems
AMDSoftware Engineer · OnsiteLast updated
Explain cache-set conflicts with address mapping, then distinguish eviction from false sharing and GPU bank conflicts so padding and layout changes target the right cause.
Explain a cache-line conflict using an address-level example, then distinguish it from false sharing and GPU shared-memory bank conflicts.
Constraints & Assumptions
The source uses the term cache-line conflict without a hardware specification. First clarify the intended mechanism. For a concrete cache-set example, assume a set-associative cache with line size L bytes, S sets, and A ways, using set index floor(address/L) mod S.
Clarifying Questions
Is the concern cache-set eviction, coherence traffic between CPU cores, or scratchpad bank serialization on a GPU? What are the access pattern, alignment, and hardware mapping?
Follow-up questions
- How can a working set smaller than total cache capacity still thrash? Why can padding help? When would padding merely increase memory use without addressing the bottleneck?
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